A number of different methods currently exist to diagnose scan chain failures in an electronic chip. See, for example, U.S. Pat. No. 3,761,695 issued Sep. 25, 1973 by Eichelberger for METHOD OF LEVEL SENSITIVE TESTING A FUNCTIONAL LOGIC SYSTEM; U.S. Pat. No. 6,308,290 B1 issued Oct. 23, 2001 to Forlenza et al. for LOOK AHEAD SCAN CHAIN DIAGNOSTIC METHOD; U.S. patent application US 2003/0131294 A1 published Jul. 10, 2003 by Motika et al. STUCK-AT FAULT SCAN CHAIN DIAGNOSTIC METHOD; U.S. patent Ser. No. 10/728,348 filed Dec. 4, 2003 by Forlenza et al. for ABIST-ASSISTED DETECTION OF SCAN CHAIN EFFECTS; U.S. patent application Ser. No. 10/767,046 filed Jan. 29, 2004 by Burdine for DIAGNOSTIC METHOD FOR DETECTION OF MULTIPLE DEFECTS IN A LEVEL SENSITIVE SCAN DESIGN (LSSD); U.S. patent application Ser. No. 10/821,160 filed Apr. 8, 2004 by Forlenza et al. for METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING DETERMINISTIC BASED BROKEN SCAN CHAIN DIAGNOSTICS; and DC SCAN DIAGNOSTIC METHOD by Forlenza et al. published in the IP. COM Journal, V4, N3, p. 117 (March 2004), all owned by the assignee of the present invention and incorporated herein by reference. Typically, however, no one method by itself is sufficient to diagnose a scan chain fail with enough confidence to send it to Physical Failure Analysis (PFA) where the failure is analyzed to determine the cause of a failure and correct the process for making the chip to prevent the failure in future runs. These methods are self-contained entities, and are not structured to interface with one another. Much time is spent determining which method(s) to utilize and exercising these methods manually. Even if a method is automated via a software medium (i.e. in a computer system), manual intervention is still required to determine which method(s) to use, to capture the results from each method, and to analyze the results from each method to determine which device to send to PFA.
Typically it takes days, and sometimes weeks, to diagnose a sufficient number of failing devices to send to PFA. During these days and weeks, the manufacturing fabrication line (fab) is still producing products which probably contain the same defects. Therefore, yields remain low, which results in significant cost-impacts. Therefore, it is critical that failing parts be diagnosed as quickly as possible to minimize the amount of defective product that continues to be processed through the wafer fab.